
IDT82V3010
T1/E1/OC3 Telecom Clock Generator with Dual Reference Inputs
Timing Characteristics
29
Feberuary 20, 2009
Figure - 13 Output Timing 1
t
F8WH
t
F0D
t
F0WL
t
F16D
t
F16WL
t
F16H
t
F16S
t
C16D
t
C16W
t
C8W
t
C4W
t
C2W
t
C2D
t
C6W
t
C6D
t
C15D
t
C15W
t
C8D
t
C4D
V
T
V
T
V
T
V
T
V
T
V
T
V
T
V
T
V
T
C1.5o
C6o
C2o
C4o
C8o
C16o
F16o
F0o
F8o
C32o
C3o
t
C32D
t
C3D
t
C3W
t
C32WH
V
T
V
T
F32o
t
F32WL
t
F32D
V
T
t
F32S
t
F32H
t
C6W
t
C4W
t
C8W
V
T
C19o
C19POS
C19NEG
V
T
V
T
t
C19D
t
C19W
V
T
t
F19WH
t
F19D
t
F19S
t
F19H
F19o
t
C19W
t
C19D
t
C19D
t
C19W
(see Note 1)